1. Field of the Invention
The present invention relates in general to a back bias generating circuit, and more particularly to a back bias generating circuit for reducing amount of electrons being injected from a pumping capacitor into a substrate so that it is suitable for high speed operation and current consumption therein can be reduced.
Description of the Prior Art
With the reference to FIG. 1, there is shown a circuit diagram of a conventional back bias generating circuit. The illustrated circuit comprises a ring oscillator IC1 for generating a signal of alternating current(AC) waveform, the output terminal of which is connected to one terminal of a pumping capacitor PC1 through inverter gates IN1-IN3. The output terminal of the inverter gate IN2 is connected commonly to gates of a PMOS transistor PM1 and an NMOS transistor NM1. The source of the PMOS transistor PM1 is connected to a power source terminal Vcc and the drain thereof is connected to the drain of the NMOS transistor NM1 and to the gate of a NMOS transistor NM2, the source of which is connected to a ground terminal Vss. The other terminal of the pumping capacitor PC1 is connected commonly to the source of the NMOS transistor NM1, the drain of the NMOS transistor NM2 and the drain of a NMOS transistor NM3, the source and gate of which are connected commonly to a back bias terminal V.sub.BB.
The operation of the conventional back bias generating circuit with the above-mentioned construction will now be described.
First, if the voltage outputted from the ring oscillator IC1 falls to a low level, the low output voltage from the ring oscillator IC1 is inverted into a high level by the inverter gate IN1 and the high-inverted voltage from the inverter gate IN1 is then again inverted into the low level by the inverter gate IN2. The wave-shaped, low voltage from the inverter gate IN2 is applied to the gates of the PMOS and NMOS transistors PM1 and NM1. As a result, the PMOS transistor PM1 is turned on while the NMOS transistor NM1 is turned off, thereby allowing the voltage at the power source terminal Vcc to be applied to the gate of the NMOS transistor NM2 through the PMOS transistor PM1. The voltage at the power source terminal Vcc turns on the NMOS transistor NM2.
On the other hand, the low output voltage from the inverter gate IN2 is inverted into a high level by the inverter gate IN3 and the high-inverted voltage from the inverter gate IN3 is then applied to the one terminal of the pumping capacitor PC1, the voltage at the other terminal of which is bypassed to the ground terminal Vss through the turned-on NMOS transistor NM2. As a result, zero volt voltage, or ground voltage appears at common connection node n1 of the other terminal of the pumping capacitor PC1 with the source and drain of the NMOS transistors NM1 and NM2. In result, the ground voltage at the common connection is applied to the drain of the NMOS transistor NM3, referred hereinafter to as switching transistor.
At this time, minus voltage at the back bias terminal V.sub.BB is applied commonly to the gate and source of the switching transistor NM3, thereby causing the switching transistor NM3 to be turned off due to a reverse bias. The turning-off of the switching transistor NM3 prevents the voltage at the back bias terminal V.sub.BB from rising.
Thereafter, if the voltage outputted from the ring oscillator IC1 rises to a high level, the high output voltage from the ring oscillator IC1 is inverted into a low level by the inverter gate IN1 and the low-inverted voltage from the inverter gate IN1 is then again inverted into the high level by the inverter gate IN2. The wave-shaped, high voltage from the inverter gate IN2 is applied to the gates of the PMOS and NMOS transistor PM1 and NM1. (As a result, the PMOS transistor PM1 and the NMOS transistor NM2 are turned off while the NMOS transistor NM1 is turned on.)
On the other hand, the high output voltage from the inverter gate IN2 is inverted into a low level by the inverter gate IN3 and the low-inverted voltage from the inverter gate IN3 is then applied to the one terminal of the pumping capacitor PC1. Because of a coupling effect of capacitor, minus voltage appears at the other terminal of the pumping capacitor PC1. Then, as the voltage at the one terminal of the pumping capacitor PC1 gradually falls to the low level, i.e., as the output voltage from the ring oscillator IC1 gradually rises to the high level, the magnitude of the minus voltage at the other terminal of the pumping capacitor PC1 becomes larger such that the minus voltage at the other terminal of the pumping capacitor PC1 is applied is applied to the drain of the switching transistor NM3. At this time, when the level of the voltage at the back bias terminal V.sub.BB is higher than that of the minus voltage at the other terminal of the pumping capacitor PC1, the switching transistor NM3 is turned on because of a normal bias. The turning-on of the switching transistor NM3 allows the voltage at the back bias terminal V.sub.BB to be bypassed therethrough. As a result, the level of the voltage at the back bias terminal V.sub.BB becomes lower.
In other words, since a large quantity of electrons generated from the pumping capacitor PC1 flows through the turned-on switching transistor NM3 to the back bias terminal V.sub.BB, the level of the voltage at the back terminal V.sub.BB becomes relatively lower.
In the conventional back bias generating circuit, however, since the lowest level of voltage generated from the pumping capacitor PC1 continues to be maintained much lower than the level of the voltage at the back bias terminal due to a potential difference V.sub.T between the drain and the source of the switching transistor NM3, electrons being injected from the junction of the pumping capacitor PC1 into the substrate are large in quantity such that they have an effect on information in cells. Namely, the large quantity of electrons results in malfunction of the cells. Also, because the voltage at the back bias terminal is always applied to the gate of the switching transistor NM3, it takes the voltage at the back bias terminal a considerably long time to fall to a desired level due to a small conductance of the switching transistor NM3. This means that the circuit is not suitable for a high speed operation.